Memory devices are important components of many integrated circuits or products having integrated circuits. Because memories are so significant to the operation of these devices, it is important that data stored in a memory device is correctly accessed. Data may be written to a memory and read from a memory using a single clock signal. Such memories enable synchronous data transfers. Data may also be asynchronously transferred in memory devices which receive data and output data using two separate asynchronous clocks. Asynchronous clocks generally not only have a different phase, but also have a different frequency.
Memory devices also have various protocols for outputting stored data. For example, an asynchronous first-in first-out (FIFO) memory is a memory device where a data sequence may be written to and retrieved from the memory in exactly the same order. Because no explicit addressing is required, the write and read operations may be completely independent and use unrelated clocks. While the concept of a FIFO is simple, the implementation of an asynchronous FIFO in an integrated circuit is often difficult. One common implementation of an asynchronous FIFO is a random access memory (RAM) having two independently clocked ports (i.e. one for writing and one for reading), and two independent address counters to steer write and read data. However, synchronizing and decoding the two ports operating at two asynchronous frequencies requires significant effort.
Further, many applications employing asynchronous FIFOs commonly require that data read from the FIFO must be re-read, and therefore the FIFO must have backup functionality. For example, backup functionality is often required in any application transferring data to an internal bus, such as any module of a circuit that pipelines data for transferring data and then restarting if data needs to be re-read. However, designing efficient, robust asynchronous FIFOs with backup capability is difficult. Conventional circuits for backing up data read from an asynchronous FIFO have significant limitations. According to a first conventional device, data backup registers, also commonly called shadow registers, are used to backup data read from the asynchronous FIFO. As shown in FIG. 1, data output from an asynchronous FIFO 102 or one of the data backup registers 104 is selected by a multiplexer 106. Consider an implementation of an asynchronous, 64-bit data width FIFO with backup functionality of 0-3 in a programmable logic device (PLD) such as a Virtex field programmable gate array (FPGA) available from Xilinx, Inc. of San Jose, Calif.
Accordingly, 192 data backup registers and 128 look-up tables (LUTs) for multiplexing the data backup register data are required for the asynchronous FIFO to be implemented in a programmable logic device (PLD). As will be described below, the use of data backup registers as shown in FIG. 1 requires significant resources when the asynchronous FIFO with backup functionality is implemented in a programmable logic device (PLD).
According to a second conventional device as shown for example in FIG. 2, a two-FIFO per data path design is implemented. A first synchronous FIFO 202 with backup capability is used to recover data when necessary. A second FIFO 204 is an asynchronous FIFO that performs the function of moving data across time-domains. Further, when employing this approach, the number of FIFOs is duplicated for each direction of data flow. The use of two pairs of FIFOs per data path not only results in greater core size, but also results in increased latency. Accordingly, conventional devices use significant resources to recover data by backing up data stored in the FIFO.
Accordingly, there is a need for an improved circuit and method of enabling reading data in an asynchronous FIFO memory with backup functionality of an integrated circuit.